This invention relates to field programmable gate arrays (“FPGAs”), and more particularly to FPGAs having integrated application specific integrated circuit (“ASIC”) fabric.
A FPGA may include a large number of relatively small modules of programmable logic. For example, each such logic module (“LM”) or logic element (“LE”) may include a four-input look-up table (“LUT”), a register (e.g., for selectively registering an output signal of the LUT), and a small amount of other circuitry (e.g., for determining whether and how the register is used, for selecting control signals for the register, etc.). The LUT may be programmable to produce an output signal that is any logical combination or function of the four inputs to the LUT. The LE may be programmable with respect to whether and how the register is used, and what control signals (e.g., clock, clock enable, clear, etc.) are selected for application to the register.
In addition to the LEs, a FPGA typically includes programmable interconnection circuitry for conveying signals to, from, and/or between the LEs in any of many different ways. This allows the relatively simple logic capabilities of individual LEs to be concatenated to perform logic tasks of considerable complexity.
It has been found helpful and economical to give the resources in FPGAs—especially large FPGAs—a hierarchical organization. For example, the LEs in a FPGA may be clustered in groups that may be called logic array blocks or LABs. The LEs in a LAB share certain resources associated with the LAB. These shared resources may include such things as LAB input multiplexers (“LIMs”), and LE input multiplexers (“LEIMs”) circuitry, which are programmable to select signals from nearby interconnection conductors so that those signals will be available as inputs to the LABs and LEs.
It has become increasingly standard in FPGA architectures to add dedicated or “hard” blocks amongst to programmable logic to add common functionality to the FPGA. The first hard blocks added to FPGAs were embedded memory. Later microprocessors and hard multipliers or digital signal processing (“DSP”) blocks were added. Other hard blocks have been considered such as crossbars or barrel shifters, and floating-point units (“FPU”), but have been rejected based on cost-benefit analyses. In general these blocks can be either full custom, standard cell, or semi-custom implementations. These hard blocks can be added to a FPGA either to make a dramatic shrink in the size of a function or to improve performance of a speed-critical block. DSP blocks, for example, achieve both. A further attraction of hard blocks is that the fixed implementation provides the benefit of a consistent implementation, reducing the effort of timing closure.
One of the main properties of hard blocks is that they tend to get dramatic benefits when used. However, it is rare that all the hard blocks are used and often these hard blocks are not used at all. This has also lead to the creation of entire families of FPGAs having, for example, “IO-rich,” “LE-rich,” “memory-rich,” and “DSP-rich” parts in order to satisfy diverse customer needs. For example, an “LE-rich” device may have one DSP column for every 10 LAB columns, while a DSP-rich device may have one DSP column every 6 LAB columns.
Some of the major hurdles in adding hard blocks to FPGAs are that: hard blocks that are a great advantage for some is just an area waste for others, it is not cost-efficient to make a family of FPGAs with too many different members and variations, and often it is not known until long after the device is defined which hard blocks should be included in a design.